ADE7566/ADE7569
POWER SUPPLY ARCHITECTURE
Each ADE7566/ADE7569 have two power supply inputs, V DD and
V BAT , and require only a single 3.3 V power supply at V DD for full
operation. A battery backup, or secondary power supply, with a
maximum of 3.6 V can be connected to the V BAT input. Internally,
the ADE7566/ADE7569 connect V DD or V BAT to V SW , which is used
to derive power for the ADE7566/ADE7569 circuitry. The V SWOUT
output pin reflects the voltage at V SW and has a maximum output
current of 6 mA. This pin can also be used to power a limited
number of peripheral components. The 2.5 V analog supply (V INTA )
and the 2.5 V supply for the core logic (V INTD ) are derived by
on-chip linear regulators from V SW . Figure 22 shows the power
supply architecture of ADE7566/ADE7569.
The ADE7566/ADE7569 provide automatic battery switchover
between V DD and V BAT based on the voltage level detected at V DD
Preliminary Technical Data
The battery switchover functionality provided by the
ADE7566/ADE7569 allows a seamless transition from V DD to
V BAT . An automatic battery switchover option ensures a stable
power supply to the ADE7566/ADE7569, as long as the external
battery voltage is above 2.75 V. It allows continuous code
execution even while the internal power supply is switching
from V DD to V BAT and back. Note that the energy metering
ADCs are not available when V BAT is being used for V SW .
Power supply monitor (PSM) interrupts can be enabled to
indicate when battery switchover occurs and when the V DD
power supply is restored (see the Power Supply Monitor
Interrupt (PSM) section.)
Switching from V DD to V BAT
The following three events switch the internal power supply
(V SW ) from V DD to V BAT :
or V DCIN . Additionally, the BCTRL input can be used to trigger a
battery switchover. The conditions for switching V SW from V DD
to V BAT and back to V DD are described in the Battery Switchover
section. V DCIN is an input pin that can be connected to a 0 V to
3.3 V dc signal. This input is intended for power supply super-
visory purposes and does not provide power to the ADE7566/
ADE7569 circuitry (see the Battery Switchover section).
V DCIN V DD V BAT V SWOUT
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V DCIN < 1.2 V. When V DCIN falls below 1.2V, V SW switches from
V DD to V BAT . This event is enabled when the BATPRG[1:0] bits
in the Battery Switchover Configuration SFR (BATPR,
0xF5) = 0b01. Setting these bits disables switchover based
on V DCIN . Battery switchover on low V DCIN is disabled by
default.
V DD < 2.75 V. When V DD falls below 2.75 V, V SW switches
from V DD to V BAT . This event is enabled when BATPRG[1:0] in
BCTRL
POWER SUPPLY
MANAGEMENT
ADC
V SW
LDO
LDO
V INTD
V INTA
MCU
ADE
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the Battery Switchover Configuration SFR (BATPR, 0xF5)
are cleared.
Rising edge on BCTRL. When the battery control pin,
BCTRL, goes high, V SW switches from V DD to V BAT . This
ADC
SPI/I 2 C
external switchover signal can trigger a switchover to V BAT
at any time. Setting bits INT1PRG[4:2] to 0bx01 in the
SCRATCHPAD
LCD
RTC
Interrupt Pins Configuration SFR (INTPR, 0xFF) enables
TEMPERATURE ADC
3.3V
Figure 22. Power Supply Architecture
BATTERY SWITCHOVER
UART
2.5V
the battery control pin.
Switching from V BAT to V DD
To switch V SW back from V BAT to V DD , all of the following events
that are enabled to force battery switchover must be false:
The ADE7566/ADE7569 monitor V DD , V BAT , and V DCIN . Automatic
battery switchover from V DD to V BAT can be configured based on
the status of V DD , V DCIN , or the BCTRL pin. Battery switchover is
enabled by default. Setting Bit 1 in the Battery Switchover
Configuration SFR (BATPR, 0xF5) disables battery switchover
so that V DD is always connected to V SW . The source of V SW is
indicated by Bit 6 in the Peripheral Configuration SFR
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V DCIN < 1.2 V and V DD < 2.75 V enabled. If the low V DCIN
condition is enabled, V SW switches to V DD after V DCIN
remains above 1.2 V and V DD remains above 2.75 V.
V DD < 2.75 V enabled. V SW switches back to V DD after V DD
has been above 2.75 V.
BCTRL enabled. V SW switches back to V DD after BCTRL is
low and the first or second bullet point is satisfied.
(PERIPH, 0xF4), which is set when V SW is connected to V DD
and cleared when V SW is connected to V BAT .
Rev. PrA | Page 26 of 136
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